Timing Main Board V1.0¶
Project description¶
The Timing Main Board interfaces the timing signals that are generated by White Rabbit (WR) to 16 RJ45 connectors according to the timing interfaces of the current DAQ boxes used at Virgo.
Figure 1: Picture of the Timing Main Board PCB V1.0
Design details¶
- Schematics (Note: Design created with Mentor Graphics using a Xpedition).
- Manufacturing files 11500.07.02 Timing Manin Board (Note: Design created with Mentor Graphics using a Xpedition).
Contacts¶
General questions about project¶
- Guido Visser -Nikhef
- Peter Jansweijer - Nikhef
Status¶
| Date | Event |
|---|---|
| 29-09-2020 | Initial Meeting with LAPP. |
| 17-03-2021 | Start working on project. Collecting main specifications. |
| 18-10-2021 | Timing Main Board PCB layout started. |
| 17-12-2021 | Layout ready. |
| 18-01-2022 | Received quotations. Ordered 4 boards. |
| 25-02-2022 | 4 boards received. |
10 January 2024
