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Timing Main Board

Project description

The Timing Main Board interfaces the timing signals that are generated by White Rabbit (WR) to 16 RJ45 connectors according to the timing interfaces of the current DAQ boxes used at Virgo.


Figure 1: Preliminary picture of the Timing Main Board PCB V1.0

Design details

Older versions and relevant information

Contacts

General questions about project

Status

Date Event
29-09-2020 Initial Meeting with LAPP.
17-03-2021 Start working on project. Collecting main specifications.
18-10-2021 Timing Main Board PCB layout started.
17-12-2021 Layout ready.
18-01-2022 Received quotations. Ordered 4 boards.
25-02-2022 4 boards received.
05-12-2023 Production first 2 TimingMainBoards V2.0 started.
18-03-2024 Received 2 TimingMainBoards V2.0.

27 March 2024

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