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Technical document
23/08/2021

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100MHzInTheLoop.png (24.3 KB) 100MHzInTheLoop.png block diagram Peter Jansweijer, 23/08/2021 13:24
SPEC7_Integration.jpg (169 KB) SPEC7_Integration.jpg Peter Jansweijer, 20/10/2021 14:16
_MG_5006_resize.JPG (132 KB) _MG_5006_resize.JPG FMCBreakout_extended Peter Jansweijer, 20/10/2021 14:21
100MHzInTheLoop.jpg (98.7 KB) 100MHzInTheLoop.jpg Peter Jansweijer, 21/10/2021 13:50
100MHzInTheLoop_PCB.jpg (152 KB) 100MHzInTheLoop_PCB.jpg Peter Jansweijer, 21/10/2021 13:55
TimingMainBoard_Preleminary.jpg (351 KB) TimingMainBoard_Preleminary.jpg Peter Jansweijer, 06/12/2021 13:05
TimingMainBoard.png (207 KB) TimingMainBoard.png Peter Jansweijer, 17/12/2021 11:03
100MHzInTheLoop_V1.0.png (284 KB) 100MHzInTheLoop_V1.0.png Peter Jansweijer, 17/12/2021 11:09
100MHzInTheLoop.jpg (293 KB) 100MHzInTheLoop.jpg PCB picture Peter Jansweijer, 16/02/2022 09:51
TimingMainBoard.JPG (326 KB) TimingMainBoard.JPG TimingMainBoard Peter Jansweijer, 28/03/2022 14:04
SPEC7_integration_v1.jpg (621 KB) SPEC7_integration_v1.jpg Peter Jansweijer, 25/04/2022 13:38
SPEC7_integration_v2.jpg (619 KB) SPEC7_integration_v2.jpg Peter Jansweijer, 30/05/2022 14:01
FrontPanel.jpg (82.2 KB) FrontPanel.jpg Front Panel Peter Jansweijer, 10/06/2022 15:41
VirgoDemonstratorWRnode.jpg (256 KB) VirgoDemonstratorWRnode.jpg Virgo Demonstrator WR-node Peter Jansweijer, 10/06/2022 15:41
100MHzInTheLoopV2.0.jpg (106 KB) 100MHzInTheLoopV2.0.jpg Block Diagram Peter Jansweijer, 05/10/2023 13:52
100MHzInTheLoopv2.0_LTC6952_InputAttenuator.jpg (93.4 KB) 100MHzInTheLoopv2.0_LTC6952_InputAttenuator.jpg 100MHzInTheLoopv2.0_LTC6952_InputAttenuator Peter Jansweijer, 16/10/2023 16:43
KVG_231030.png (52.4 KB) KVG_231030.png Peter Jansweijer, 28/11/2023 10:37
DAC20-1.jpg (70.3 KB) DAC20-1.jpg DAC20 PCB Peter Jansweijer, 28/11/2023 10:55
dac20-2.jpg (65.3 KB) dac20-2.jpg DAC20 fitted at U9 on 100MHzInTheLoop Peter Jansweijer, 28/11/2023 10:56
100MHzInTheLoopV2_0.jpg (187 KB) 100MHzInTheLoopV2_0.jpg 100MHzInTheLoopV2.0 Peter Jansweijer, 15/01/2024 11:20
AddedPhaseNoiseInTrackPhase.png (60.6 KB) AddedPhaseNoiseInTrackPhase.png DAC16_AddedPhaseNoiseInTrackPhase Peter Jansweijer, 15/01/2024 11:34
100MHzInTheLoopV3_0_3D.jpg (205 KB) 100MHzInTheLoopV3_0_3D.jpg 100MHzInTheLoopV3.0 #D Peter Jansweijer, 17/01/2024 12:09
PhaseNoise_Comparison.bmp (3.62 MB) PhaseNoise_Comparison.bmp FPGA Phase Noise Comparison Peter Jansweijer, 26/02/2024 11:05
TimingMainBoardV2_0.jpg (143 KB) TimingMainBoardV2_0.jpg Peter Jansweijer, 26/03/2024 16:35
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