General

Profile

Peter Jansweijer

  • Email: peterj@nikhef.nl
  • Technical group:

    ET CT EXTERNAL OR PROJECT NAME

  • Internship/Student: No
  • Registered on: 29/10/2015
  • Last connection: 27/10/2021

Issues

Projects

Activity

21/10/2021

14:13 ETpathfinder Timing TimingMainBoard_211021.pdf
14:03 ETpathfinder Timing 11500.04.02.0_SCH.PDF
schematics 100MHzInTheLoop
14:00 ETpathfinder Timing 11500.04.02.0_PCB.ZIP
11500.04.02 100MHzInTheLoop
13:55 ETpathfinder Timing 100MHzInTheLoop_PCB.jpg
13:50 ETpathfinder Timing 100MHzInTheLoop.jpg

20/10/2021

14:21 ETpathfinder Timing _MG_5006_resize.JPG
FMCBreakout_extended
14:16 ETpathfinder Timing SPEC7_Integration.jpg

20/09/2021

15:34 EMPIR-WRITE FPGA_PhaseNoise_Draft.pdf

26/08/2021

15:48 ETpathfinder Timing 11500.03.02.0_SCH.PDF
Schematics FMC Breakout Board Extended
14:30 ETpathfinder Timing 11500.03.02.0.PCB.ZIP
11500.03.02 FMC Breakout Board Extended

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