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Andrea Borga

PLDa MIG coregen

07/01/2016 10:20

Step by step guide to create a Memory Interface Generatar (MIG) core for DDR2 RAMs

CROC MIG coregen

07/01/2016 10:21

Step by step guide to create a Memory Interface Generator (MIG) core for DDR3 RAMs

TWEPP paper on the CRORC

07/01/2016 10:47

Conference paper on the hardware platform, i.e. the CROC, also used as RobinNP module for the ROS

TIPP paper on the ROS

07/01/2016 10:49

Conference paper on the ROS Gen III system

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